Datasheet

Register Description
R
Datasheet 133
3.9.13 HPLLCC – HPLL Clock Control Register (Device #0)
Address Offset: C0–C1h
Default Value: 00h
Access: Read Only
Size: 16 bits
Bit Description
15:11 Reserved
10 HPLL VCO Change Sequence Initiate Bit:
Software must Write a 0 to clear this bit and then Write a 1 to initiate sequence again.
9 Hphase Reset Bit:
1 = Assert
0 = Deassert (default)
8:2 Reserved
1:0 HPLL Clock Control:
See the following tables below
Table 34. Intel
®
852GME GMCH and Intel
®
852PM MCH Configurations
Straps Read Through
HPLLCC[2:0]:
D0:F3:Register Offset
C0-C1h, bits[2:0]
FSB
Frequency
System
Memory
Frequency
GFX Core
Clock – Low
(Render Core
Frequency
only)
Intel
®
852GME
GMCH Only
GFX Core Clock –
High (Render Core
Frequency &
Display Core
Frequency)
Intel
®
852GME
GMCH Only
000 400 MHz 266 MHz 133 MHz 200 MHz
001 400 MHz 200 MHz 100 MHz 200 MHz
010 400 MHz 200 MHz 100 MHz 133 MHz
011 400 MHz 266 MHz 133 MHz 266 MHz
100 533 MHz 266 MHz 133 MHz 200 MHz
101 533 MHz 266 MHz 133 MHz 266 MHz
110 533 MHz 333 MHz 166 MHz 266 MHz
111 400 MHz 333 MHz 166 MHz 250 MHz