Datasheet

Register Description
R
122 Datasheet
3.8.17 DTC – DRAM Throttling Control Register (Device #0,
Function #1)
Offset Address: A0–A3h
Default Value: 00000000h
Access: Read/Write/Lock
Size: 32 bits
Throttling is independent for system memory banks, GMCH Writes, and Thermal Sensor Trips.
Read and Write Bandwidth is measured independently for each bank. If the number of Octal -
Words (16 bytes) Read/Written during the window defined below (Global DDR SDRAM
Sampling Window: GDSW) exceeds the DDR SDRAM Bandwidth Threshold, then the DDR
SDRAM Throttling mechanism will be invoked to limit DDR SDRAM Reads/Writes to a lower
bandwidth checked over smaller time windows. The throttling will be active for the remainder of
the current GDSW and for the next GDSW after which it will return to Non-Throttling mode. The
throttling mechanism accounts for the actual bandwidth consumed during the sampling window,
by reducing the allowed bandwidth within the smaller throttling window based on the bandwidth
consumed during the sampling period. Although bandwidth from/to independent rows and
GMCH Write bandwidth is measured independently, once Tripped all transactions except high
priority graphics Reads are subject to throttling.
Bit Description
31:28 DDR SDRAM Throttle Mode (TMODE):
Four bits control which mechanisms for Throttling are enabled in an “OR” fashion.
Counter-based Throttling is lower priority than Thermal Trips Throttling when both are
enabled and Tripped. Counter-based trips point Throttling values and Thermal-based
Trip Point Throttling values are specified in this register.
0000 = Throttling turned off. This is the default setting. All Counters are off.
0001 = Only GMCH Thermal Sensor based Throttling is enabled. If GMCH Thermal
Sensor is Tripped, Write Throttling begins based on the setting in WTTC.
0010 = Only Rank Thermal Sensor based Throttling is enabled. When the external
SO-DIMM Thermal sensor is Tripped, DDR SDRAM Throttling begins based on the
setting in RTTC.
0011 = Both Rank and GMCH Thermal Sensor based throttling is enabled. When the
external SO-DIMM Thermal Sensor is Tripped DDR SDRAM Throttling begins based on
the setting in RTTC. If the GMCH Thermal Sensor is Tripped, Write Throttling begins
based on the setting in WTTC.
0100 = Only the GMCH Write Counter mechanism is enabled. When the threshold set
in the GDT field is reached, DDR SDRAM Throttling begins based on the setting in
WCTC.
0101 = GMCH Thermal Sensor and GMCH Write DDR SDRAM Counter mechanisms
are both enabled. If the GMCH Write DDR SDRAM Counter mechanism threshold is
reached, DDR SDRAM Throttling begins based on the setting in WCTC. If the GMCH
Thermal Sensor is tripped, DDR SDRAM Throttling begins based on the setting in
WTTC. If both threshold mechanisms are tripped, the DDR SDRAM Throttling begins
based on the settings in WTTC.
0110 = Rank Thermal Sensor and GMCH Write DDR SDRAM Counter mechanisms
are both enabled. If the GMCH Write DDR SDRAM Counter mechanism threshold is
reached, DDR SDRAM Throttling begins based on setting in WCTC. If the external SO-
DIMM Thermal Sensor is tripped, Rank DDR SDRAM throttling begins based on the
setting in RTTC.