Datasheet

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12 Datasheet
Intel
®
852PM Chipset MCH Features

Processor/Host Bus Support
⎯ Mobile Intel
®
Pentium
®
4 processor
supporting Hyper-Threading Technology
†
on 90-nm process technology
⎯ Mobile Intel
®
Pentium
®
4 processor
⎯ Intel
®
Celeron
®
processor
⎯ Intel
®
Celeron
®
D processor on 90 nm
process and in the 478-pin package
⎯ Source synchronous double pumped
Address (2X)
⎯ Source synchronous quad pumped Data
(4X)
⎯ Supports a subset of the Enhanced Mode
Scalable Bus Protocol
⎯ Intel Pentium 4 processor system bus
interrupt delivery
⎯ Supports processor system bus at 400 & 533
MHz
⎯ Supports host Dynamic Bus Inversion
(DBI)
⎯ Supports 32-bit host bus addressing
⎯ 8-deep, In-Order-Queue
⎯ AGTL+ bus driver technology with
integrated AGTL termination resistors
⎯ Supports Enhanced Intel SpeedStep
®
technology

Memory System
⎯ Directly supports one DDR SDRAM
channel, 64-bits wide
⎯ Supports 200/266/333 MHz DDR SDRAM
devices with max of 2 Double-Sided SO-
DIMMs with unbuffered PC1600/PC2100
DDR SDRAM.
⎯ Supports 128-Mbit, 256-Mbit, and 512-Mbit
technologies
⎯ System memory support up to 1-GB with
x16 devices and up to 2-GB with high
density 512-Mbit devices
⎯ All supported devices have 4 banks
⎯ Supports up to 16 simultaneous open pages
⎯ ECC only supported with internal graphics

System Interrupts
⎯ Supports Intel 8259 and processor system
bus interrupt delivery mechanism
⎯ Supports interrupts signaled as upstream
Memory Writes from PCI and hub interface
⎯ MSI sent to the CPU through the processor
system bus
⎯ IOxAPIC in ICH4-M provides redirection
for upstream interrupts to the system bus

Accelerated Graphics Port (AGP) interface
⎯ Supports a single AGP device
⎯ Supports AGP 2.0 including 1X, 2X, and 4X
AGP data transfers and 2X/4X

Fast Write protocol
⎯ Supports only 1.5 V AGP electricals
⎯ 32 deep AGP request queue
⎯ PCI semantic (FRAME# initiated) accesses
to DDR SDRAM are snooped
⎯ AGP semantic (PIPE# and SBA) accesses to
DDR SDRAM are not snooped
⎯ Hierarchical PCI configuration mechanism
⎯ Delayed transaction support
⎯ 32-bit upstream address support for inbound
AGP and PCI cycles
⎯ 32-bit downstream address support for
outbound PCI and Fast Write cycles
⎯ AGP Busy/Stop Protocol

Hub interface to ICH4-M
⎯ 266 MB/s point-to-point hub interface to
ICH4-M
⎯ 66 MHz base clock

Power Management
⎯ SMRAM space remapping to A0000h (128
kB)
⎯ Supports extended SMRAM space above
256-MB, additional 1-MB TSEG from Top
of Memory, cacheable (cacheability
controlled by CPU)
⎯ APM Rev 1.2 compliant power management
⎯ Supports Suspend to System Memory (S3),
Suspend to Disk (S4) and Hard Off/Total
Reboot (S5)
⎯ ACPI 1.0b, 2.0 Support

Package
⎯ 732-pin Micro-FCBGA (37.5 x 37.5 mm)