Datasheet

Register Description
R
Datasheet 115
Bit Description
3:2 DDR SDRAM RAS# to CAS# Delay (tRCD): This bit controls the number of clocks
inserted between a Row Activate command and a Read or Write command to that row.
Encoding tRCD
00: 4 DDR SDRAM Clocks (DDR 333 SDRAM)
01: 3 DDR SDRAM Clocks
10: 2 DDR SDRAM Clocks
11: Reserved
1:0 DDR SDRAM RAS# Precharge (tRP): This bit controls the number of clocks that are
inserted between a row precharge command and an activate command to the same row.
Encoding tRP
00: 4 DDR SDRAM Clocks (DDR 333 SDRAM)
01: 3 DDR SDRAM Clocks
10: 2 DDR SDRAM Clocks
11: Reserved