Datasheet

Register Description
R
106 Datasheet
3.8.3 PCICMD – PCI Command Register (Device #0, Function #1)
Address Offset: 04-05h
Default Value: 0006h
Access: Read Only, Read/Write
Size: 16 bits
Since GMCH/MCH Device #0 does not physically reside on PCI_A, many of the bits are not
implemented.
Bit Description
15:10 Reserved
9 Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do
fast back-to-back Write. Since Device #0 is strictly a target, this bit is not implemented
and is hardwired to 0. Writes to this bit position have no affect.
8 SERR Enable (SERRE): SERR# is not implemented by Function #1 of Device #0 of the
GMCH/MCH and this bit is hardwired to 0. Writes to this bit position have no effect.
7 Address/Data Stepping Enable (ADSTEP): Address/data stepping is not implemented
in the GMCH/MCH, and this bit is hardwired to 0. Writes to this bit position have no
effect.
6 Parity Error Enable (PERRE): PERR# is not implemented by GMCH/MCH and this bit
is hardwired to 0. Writes to this bit position have no effect.
5 VGA Palette Snoop Enable (VGASNOOP): The GMCH/MCH does not implement this
bit and it is hardwired to a 0. Writes to this bit position have no effect.
4 Memory Write and Invalidate Enable (MWIE): The GMCH/MCH will never issue
Memory Write and Invalidate commands. This bit is therefore hardwired to 0. Writes to
this bit position will have no effect.
3 Special Cycle Enable (SCE): The GMCH/MCH does not implement this bit and it is
hardwired to a 0. Writes to this bit position have no effect.
2 Bus Master Enable (BME): The GMCH/MCH is always enabled as a master on hub
interface. This bit is hardwired to a 1. Writes to this bit position have no effect.
1 Memory Access Enable (MAE): The GMCH/MCH always allows access to main
system memory. This bit is not implemented and is hardwired to 1. Writes to this bit
position have no effect.
0 I/O Access Enable (IOAE): This bit is not implemented in the GMCH/MCH and is
hardwired to a 0. Writes to this bit position have no effect.