Datasheet

98 Datasheet

4.9.15 PWRMG – DRAM Controller Power Management Control

Address Offset: 68h-6Bh

Default Value: 00000000h

Access: Read/Write

Size: 32 bits

Bit Description

31:24 Reserved

23:20 Row State Control: This field determines the number of clocks the System Memory Controller will

remain in the idle state before it begins pre-charging all pages or powering down rows.

- PDEn: Power Down Enable

- PCEn: Page Close Enable

- TC: Timer Control

PDEn(23): PCEn(22): TC(21:20) Function

0 0 XX All Disabled

0 1 XX Reserved

1 0 XX Reserved

1 1 00 Immediate Precharge and Powerdown

1 1 01 Reserved

1 1 10 Precharge and Power Down after 16 DDR SDRAM Clocks

1 1 11 Precharge and Power Down after 64 DDR SDRAM Clocks

19:16 Reserved

15 Self Refresh GMCH Memory Interface Data Bus Power Management Optimization Enable:

0 = Enable

1 = Disable

14 CS# Signal Drive Control:

0 = Enable CS# Drive Control, based on rules described in DRC bit 12.

1 = Disable CS# Drive Control, based on rules described in DRC bit 12.

13 Self Refresh GMCH Memory Interface Data Bus Power Management:

0 = In Self Refresh Mode GMCH Power Management is Enabled.

1 = In Self Refresh Mode the GMCH Power Management is Disabled.

12 Dynamic Memory Interface Power Management:

0 = Dynamic Memory Interface Power Management Enabled.

1 = Dynamic Memory Interface Power Management Disabled.