Datasheet

Register Description
R
Datasheet 85
4.8.33 LPTT – Low Priority Transaction Timer Register (Device #0)
Address Offset: BDh
Default Value: 00h
Access: Read/Write
Size: 8 bits
LPTT is an 8-bit register similar in a function to AMTT. This register is used to control the
minimum tenure on the AGP for low priority data transaction (both reads and writes) issued using
PIPE# or SB mechanisms.
The number of clocks programmed in the LPTT represents the guaranteed time slice (measured in
66 MHz clocks) allotted to the current low priority AGP transaction data transfer state. This does
not necessarily apply to a single transaction but it can span over multiple low-priority transactions
of the same type. After this time expires the AGP arbiter may grant the bus to another agent if
there is a pending request. The LPTT does not apply in the case of high-priority request where
ownership is transferred directly to high-priority requesting queue. The default value of LPTT is
00h and disables this function. The LPTT value can be programmed with 8 clock granularity. For
example, if the LPTT is programmed to 10h, then the selected value corresponds to the time
period of 16 AGP (66 MHz) clocks.
Bit Description
7:3 Low Priority Transaction Timer Count Value. The number of clocks programmed in these bits
represents the guaranteed time slice (measured in eight 66 MHz clock granularity) allotted to the
current low priority AGP transaction data transfer state.
2:0 Reserved.
4.8.34 HEM – Host Error Control, Status and Observation (Device
#0)
Address Offset: F0–F3h
Default Value: 0000000000h
Access: Read/Write, RO
Size: 32 bits
Bit Description
31 Detected HADSTB1# Glitch (ASTB1GL): This bit is set when the GMCH has detected a glitch on
address strobe HADSTB1#. Software must write a 1 to clear this status bit.
30 Detected HADSTB0# Glitch (ASTB0GL): This bit is set when the GMCH has detected a glitch on
address strobe HADSTB0#. Software must write a 1 to clear this status bit.
29 Detected HDSTB3# Glitch (DSTB3GL): This bit is set when the GMCH has detected a glitch on data
strobe pair HDSTB3#. Software must write a 1 to clear this status bit.
28 Detected HDSTB2# Glitch (DSTB2GL): This bit is set when the GMCH has detected a glitch on data
strobe pair HDSTB2#. Software must write a 1 to clear this status bit.
27 Detected HDSTB1# Glitch (DSTB1GL): This bit is set when the GMCH has detected a glitch on data
strobe pair HDSTB1#. Software must write a 1 to clear this status bit.