Datasheet

Register Description
R
78 Datasheet
4.8.24 SHIC – Secondary Host Interface Control Register (Device
#0)
Address Offset: 74-77h
Default Value: 00006010h
Access: Read Only, Read/Write
Size: 32 bits
Bit Description
31 Reserved
30 BREQ0# Control of FSB Address and Control bus power management:
0 = Disable FSB address and control bus power management.
1 = Enable FSB address and control bus power management.
29:28 Reserved
27 On Die Termination (ODT) Gating Disable:
0 = Enable.
1 = Disable.
26:7 Reserved
6 FSB Data Bus Power Management Control:
0 = FSB Data Bus Power Management disabled (Default).
1 = FSB Data Bus Power Management enabled
5 Reserved
4:3 DPWR# Control.
00 = DPWR# pin is always asserted.
10 = DPWR# pin is asserted at least 2 clocks before read data is returned to the processor on the FSB
(2 clocks before DRDY# asserted). This is default setting.
01 = DPWR# is always de-asserted.
11 = Reserved
2 C2 state GMCH FSB Interface Power Management Control:
0 = Power Management Disabled in C2 state
1 = Power Management Enabled in C2 state