Datasheet

Datasheet 73

4.8.19 ESMRAMC – Extended System Management RAM Control

(Device #0)

Address Offset: 61h

Default Value: 38h

Access: Read/Write/Lock

Size: 8 bits

The Extended SMRAM register controls the configuration of Extended SMRAM Space. The

Extended SMRAM (E_SMRAM) Memory provides a Write-Back cacheable SMRAM Memory

Space that is above 1 MB.

Bit Description

7 H_SMRAM_EN (H_SMRAME): Controls the SMM Memory Space location (i.e., above 1 MB or below

1 MB). When G_SMRAME is 1 and H_SMRAME this bit is set to 1, the high SMRAM Memory Space

is enabled. SMRAM accesses from 0FEDA0000h to 0FEDBFFFFh are remapped to DDR SDRAM

address 000A0000h to 000BFFFFh.

Once D_LCK is set, this bit becomes Read Only.

6 E_SMRAM_ERR (E_SMERR): This bit is set when CPU accesses the defined DDR SDRAM ranges

in Extended SMRAM (High system memory and T-segment) while not in SMM Space. It is software’s

responsibility to clear this bit. The software must Write a 1 to this bit to clear it.

5 SMRAM_Cache (SM_CACHE): GMCH forces this bit to 1.

4 SMRAM_L1_EN (SM_L1): GMCH forces this bit to 1.

3 SMRAM_L2_EN (SM_L2): GMCH forces this bit to 1.

2:1 Reserved

0 TSEG_EN (T_EN): Enabling of SMRAM Memory (TSEG, 1 Mbytes of additional SMRAM Memory) for

Extended SMRAM Space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to

appear in the appropriate physical address space.

Once D_LCK is set, this bit becomes Read Only.