Datasheet

Datasheet 65

4.8.11 CAPPTR – Capabilities Pointer Register

Bit Description

7:0 Pointer to the offset of the first capability ID register block: In this case the first capability is the

Product-Specific Capability, which is located at offset 40h.

4.8.12 CAPID – Capability Identification Register (Device #0)

Address Offset: 40h – 44h

Default: chipset dependent

Access: Read Only

Size 40 bits

The Capability Identification Register uniquely identifies chipset capabilities as defined in the

table below. The bits in this register are intended to define a capability ceiling for each feature,

not a capability select. The capability selection for each feature is implemented elsewhere. The

mechanism to select the capability for each feature must comprehend these Capability registers

and not allow a selected setting above the ceiling specified in these registers. The BIOS must read

this register to identify the part and comprehend the capabilities specified within when

configuring the effected portions of the GMCH.

The default setting, in most cases, allows the maximum capability. Exceptions are noted in the

individual bits. This register is Read Only. Writes to this register have no effect.

Bit Description

39:37 Capability ID [2:0]:

000 = Intel 855GME GMCH

001-011 = Reserved

100 = Intel 855GM GMCH

101-111 = Reserved

36:28 Reserved

27:24 CAPREG Version: This field has the value 0001b to identify the first revision of the CAPREG definition.

23:16 Cap_length: This field has the value 05h indicating the structure length.

15:0 Reserved