Datasheet

58 Datasheet

Bit Descriptions

31:0 Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1, then any I/O access to

the CONFIG_DATA register will be mapped to Configuration Space using the contents of

CONFIG_ADDRESS.

4.7 VGA I/O Mapped Registers

If Device #2 is enabled, and Function #0 within Device #2 is enabled for VGA, and IO_EN is set

within Function #0 then GMCH claims a set of I/O registers for legacy VGA function. Table 22

lists direct CPU Access registers and Table 23 lists registers that are Index – Data registers that

are used to access Internal VGA registers.

Table 22. VGA I/O Mapped Register List

Name Function Read @ Write @

ST00 VGA Input Status Register 0 3C2h ⎯

ST01 VGA Input Status Register 1 3BAh/3Dah ⎯

FCR VGA Feature Control Register 3CAh 3BAh/3DAh

MSR VGA Miscellaneous Status/Output Register 3CCh 3C2h

Table 23. Index – Data Registers

Name Function Index IO Data IO

SRX Sequencer Registers 3C4 3C5

GRX Graphics Controller Registers 3CE 3CF

ARX Attribute Control Registers 3C0 3C0: Write

3C1: Read

DACMASK Pixel Data Mask Register -- 3C6h

DACSTATE DAC State Register -- 3C7 Read Only

DACRX Palette Read Index Register 3C7 Write Only --

DACWX Palette Write Index Register 3C8 Write Only

DACDATA Palette Data Register 3C9

CRX CRT Registers 3B4/3D4

(MDA/CGA)

3B5/3D5

(MDA/CGA)