Datasheet

Signal Descriptions
R
Datasheet 41
3.6 Internal Graphics Display Signals
The IGD has support for a dedicated LVDS LCD Flat Panel Interface, DVOB/C interfaces, and an
Analog CRT port.
3.6.1 Dedicated LVDS LCD Flat Panel Interface
Table 12. Dedicated LVDS LCD Flat Panel Interface Signal Descriptions
Name Type Voltage Description
ICLKAP O
LVDS
1.25 V ±225 mV Channel A differential clock pair output (true): 245–800 MHz
ICLKAM O
LVDS
1.25 V ±225 mV Channel A differential clock pair output (compliment): 245–
800 MHz.
IYAP[3:0] O
LVDS
1.25 V ±225 mV Channel A differential data pair 3:0 output (true): 245–800 MHz.
IYAM[3:0] O
LVDS
1.25 V ±225 mV Channel A differential data pair 3:0 output (compliment): 245–
800 MHz.
ICLKBP O
LVDS
1.25 V ±225 mV Channel B differential clock pair output (true): 245–800 MHz.
ICLKBM O
LVDS
1.25 V ±225 mV Channel B differential clock pair output (compliment): 245–
800 MHz.
IYBP[3:0] O
LVDS
1.25 V ±225 mV Channel B differential data pair 3:0 output (true): 245–800 MHz.
IYBM[3:0] O
LVDS
1.25 V ± 225 mV Channel B differential data pair 3:0 output (compliment): 245–
800 MHz.