Datasheet

R
4 Datasheet
4.1
Conceptual Overview of the Platform Configuration Structure ............................ 51
4.2 Nomenclature for Access Attributes.....................................................................52
4.3 Standard PCI Bus Configuration Mechanism.......................................................53
4.4 Routing Configuration Accesses ..........................................................................53
4.4.1 PCI Bus #0 Configuration Mechanism..................................................53
4.4.2 Primary PCI and Downstream Configuration Mechanism....................54
4.4.3 AGP/PCI_B Bus Configuration Mechanism.......................................... 54
4.5 Register Definitions .............................................................................................. 55
4.6 I/O Mapped Registers ..........................................................................................56
4.6.1 CONFIG_ADDRESS – Configuration Address Register......................56
4.6.2 CONFIG_DATA – Configuration Data Register ...................................57
4.7 VGA I/O Mapped Registers.................................................................................. 58
4.8 Intel
®
855GM/GME GMCH Host-Hub Interface Bridge Device Registers
(Device #0, Function #0) ......................................................................................59
4.8.1 VID – Vendor Identification Register ....................................................60
4.8.2 DID – Device Identification Register.....................................................60
4.8.3 PCICMD – PCI Command Register .....................................................61
4.8.4 PCI Status Register ..............................................................................62
4.8.5 RID – Register Identification.................................................................63
4.8.6 SUBC – Sub Class Code Register .......................................................63
4.8.7 BCC – Base Class Code Register........................................................63
4.8.8 HDR – Header Type Register...............................................................64
4.8.9 SVID – Subsystem Vendor Identification Register ............................... 64
4.8.10 SID – Subsystem Identification Register ..............................................64
4.8.11 CAPPTR – Capabilities Pointer Register.............................................. 65
4.8.12 CAPID – Capability Identification Register (Device #0)........................65
4.8.13 GMC – GMCH Miscellaneous Control Register (Device #0)................ 66
4.8.14 GGC – GMCH Graphics Control Register (Device 0) .......................... 67
4.8.15 DAFC – Device and Function Control Register (Device 0) ..................68
4.8.16 FDHC – Fixed DRAM Hole Control Register (Device #0) .................... 68
4.8.17 PAM(6:0) – Programmable Attribute Map Register (Device #0) .......... 69
4.8.18 SMRAM – System Management RAM Control Register (Device #0) ..72
4.8.19 ESMRAMC – Extended System Management RAM Control
(Device #0)............................................................................................ 73
4.8.20 ERRSTS – Error Status Register (Device #0)......................................74
4.8.21 ERRCMD – Error Command Register (Device #0) ..............................75
4.8.22 SMICMD – SMI Error Command Register (Device #0)........................76
4.8.23 SCICMD – SCI Error Command Register (Device 0)........................... 77
4.8.24 SHIC – Secondary Host Interface Control Register (Device #0)..........78
4.8.25 ACAPID – AGP Capability Identifier Register (Device #0)...................79
4.8.26 AGPSTAT – AGP Status Register (Device #0) .................................... 80
4.8.27 AGPCMD – AGP Command Register (Device #0)............................... 81
4.8.28 AGPCTRL – AGP Control Register (Device #0) .................................. 82
4.8.29 AFT – AGP Functional Test Register (Device #0)................................82
4.8.30 APSIZE – Aperture Size (Device #0)....................................................83
4.8.31 ATTBASE – Aperture Translation Table Base Register (Device #0) ...84
4.8.32 AMTT – AGP Interface Multi-Transaction Timer Register (Device #0) 84
4.8.33 LPTT – Low Priority Transaction Timer Register (Device #0)..............85
4.8.34 HEM – Host Error Control, Status and Observation (Device #0) ......... 85
4.9 Intel
®
855GM/GME GMCH Main Memory Control, Memory I/O Control Registers
(Device #0, Function #1) ......................................................................................86
4.9.1 VID – Vendor Identification Register ....................................................87