Datasheet

Signal Descriptions
R
Datasheet 39
3.4 Hub Interface Signals
Table 10. Hub Interface Signals
Signal Name Type Description
HL[10:0] I/O
Hub
Packet Data: Data signals used for HI read and write operations.
HLSTB I/O
Hub
Packet Strobe: One of two differential strobe signals used to transmit or receive
packet data over HI.
HLSTB# I/O
Hub
Packet Strobe Complement: One of two differential strobe signals used to transmit or
receive packet data over HI.
3.5 Clocks
Table 11. Clock Signals
Signal Name Type Description
Host Processor Clocking
BCLK
BCLK#
I
CMOS
Differential Host Clock In: These pins receive a buffered host clock from the
external clock synthesizer. This clock is used by all of the GMCH logic that are in
the Host clock domain (Host, Hub and system memory). The clock is also the
reference clock for the graphics core PLL. This is a low voltage differential input.
System Memory Clocking
SCK[5:0] O
SSTL_2
Differential DDR SDRAM Clock: SCK and SCK# pairs are differential clock
outputs. The crossing of the positive edge of SCK and the negative edge of SCK# is
used to sample the address and control signals on the DDR SDRAM. There are 3
pairs to each SO-DIMM.
NOTE: ECC error detection is supported by the SCK[2] and SCK[5] signals.
SCK[5:0]# O
SSTL_2
Complementary Differential DDR SDRAM Clock: These are the complimentary
differential DDR SDRAM clock signals.
NOTE: ECC error detection is supported by the SCK[2]# and SCK[5]# signals.
DVO/Hub Input Clocking
GCLKIN I
CMOS
Input Clock: 66 MHz, 3.3 V input clock from external buffer DVO/Hub interface.
DVO Clocking
DVOBCLK
DVOBCLK#
O
DVO
Differential DVO Clock Output: These pins provide a differential pair reference
clock that can run up to 165 MHz.
DVOBCLK corresponds to the primary clock out.
DVOBCLK# corresponds to the primary complementary clock out.
DVOBCLK and DVOBCLK# should be left as NC (“Not Connected”) if the DVO B
port is not implemented.