Datasheet

Intel® 855GM/GME GMCH Strap Pins
R
Datasheet 201
10 Intel
®
855GM/GME GMCH Strap
Pins
10.1 Strapping Configuration
Table 54. Strapping Signals and Configuration
Pin Name Strap Description Configuration I/F Type Buffer Type
HSYNC XOR Chain Test Low = Normal Ops (Default)
High = XOR Test On
GPIO OUT
VSYNC ALL Z Test Low = Normal Ops (Default)
High = AllZ Test On
GPIO OUT
LCLKCTLB VTT Voltage Select High = 1.05 V – Intel Pentium
M Processor / Intel Celeron M
Processor
GPIO OUT
DVODETECT DVO Select (If
DVODETECT=0 during
Reset, ADDID[7:0] is
latched to the ADDID
Register)
(1)
Low = DVO (Default)
High = Reserved
DVO BI
GST[2] Clock Config: Bit_2
(1)
GST[1] Clock Config: Bit_1
(1)
GST[0] Clock Config: Bit_0
(1)
Please refer to Device #0
Function #3 (HPLLCC
Register) for proper GST[2:0]
settings
DVO Out:
0) Before CPURST#, there is
internal pull-down
1) Just out of CPURST#:
These pins are Hi-Z
2) C3: these pins are Hi-Z
3) S1-M: these pins are Hi-Z
4) Internal GFX D1/D3: these
pins are Hi-Z
5) S3: these pins are Power
down
6) S4/S5: these pins are
Power down
NOTES:
1. External pull-ups/downs will be required on the board to enable the non-default state of the straps.
Note: All strap signals are sampled with respect to the leading edge of the Intel 855GM/GME GMCH
PWROK In signal.
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