Datasheet

Introduction
R
20 Datasheet
Term Description
or destined for the ICH4-M are generally referred to as “Hub interface cycles.”
Hub cycles originating from or destined for the primary PCI interface on are
sometimes referred to as “Hub interface/PCI cycles”
Host This term is used synonymously with processor
IGD Integrated Graphics Device
Intel 855GM/GME
GMCH
Refers to the GMCH component. Throughout this datasheet, the Intel
855GM/GME GMCH will be referred to as the GMCH.
Intel 82801DBM ICH4-M The component contains the primary PCI interface, LPC interface, USB 2.0,
ATA-100, AC’97, and other I/O functions. It communicates with the Intel
855GM/GME GMCH over a proprietary interconnect called the Hub interface.
Throughout this datasheet, the Intel 82801DBM ICH4-M component will be
referred to as the ICH4-M
Intel Pentium M
Processor
Refers to the Intel Pentium M Processor and Intel Pentium M Processor
on 90nm process with 2-MB L2 Cache. Intel Pentium M Processor will
reference both processors unless specified
IPI Inter Processor Interrupt
LFP Local Flat Panel
LVDS Low Voltage Differential Signals used for interfacing to LCD Flat Panels
MSI Message Signaled Interrupts. MSI allow a device to request interrupt service
via a standard memory write transaction instead of through a hardware signal
FSB Front side bus. Connection between Intel 855GM/GME GMCH and the CPU.
Also known as the Host interface
PWM Pulse Width Modulation
SSC Spread Spectrum Clocking
System Bus Processor-to-Intel 855GM/GME GMCH interface. The Enhanced mode of the
Scalable bus is the P6 Bus plus enhancements, consisting of source
synchronous transfers for address and data, and system bus interrupt delivery.
The Intel Pentium M processor, Intel Pentium M on 90nm process with 2-MB L2
Cache
and Intel Celeron M processor implement a subset of Enhanced mode.
UMA Unified Memory Architecture with graphics memory for the IGD inside system
memory
VDL Video Data Link