Datasheet

Video Filter Capacitors and Ferrite Bead Arranged in a
PI Configuration (One PI Filter Testability)
R
186 Datasheet
9.1 XOR Test Mode Entry
Figure 11. XOR Chain Test Mode Entry Events Diagram
powerok
LCLKCTLA
HSYNC
Don't care
Don't care
RSTIN# (P C I reset)
Don't care
VSYNC
NOTE: HSYNC and LCLKCTLA = XOR Chain Test Mode Activation; No clock is required for XOR Chain Test
Mode. A minimum of 50 ns PWROK assertion prior to RSTIN# assertion is recommended. A minimum
of 10 ns VSYNC/HSYNC/LCLKCTLA assertion prior to PWROK assertion is recommended.
Figure 12. ALLZ Test Mode Entry Events Diagram
powerok
LCLKCTLA
Don't care
HSYNC
VSYNC
Don't care
Don't care
RSTIN# (PC I reset)
NOTE: VSYNC and LCLKCTLA = ALL Z Test Mode Activation; No clock is required for ALLZ Test Mode
Activation. A minimum of 50 ns PWROK assertion prior to RSTIN# assertion is recommended. A
minimum of 10 ns VSYNC/HSYNC/LCLKCTLA assertion prior to PWROK assertion is recommended.