Datasheet

Register Description
R
Datasheet 121
4.11.20 PMCAP – Power Management Capabilities Register (Device
#2)
Address Offset: D2h−D3h
Default Value: 0221h
Access: Read Only
Size: 16 bits
Bit Description
15:11 PME Support: This field indicates the power states in which the IGD may assert PME#. Hardwired to 0
to indicate that the IGD does not assert the PME# signal.
10:6 Reserved
5 Device Specific Initialization (DSI): Hardwired to 1 to indicate that special initialization of the IGD is
required before generic class device driver is to use it.
4 Auxiliary Power Source: Hardwired to 0.
3 PME Clock: Hardwired to 0 to indicate IGD does not support PME# generation.
2:0 Version: Hardwired to 001b to indicate there are 4 bytes of power management registers implemented.
4.11.21 PMCS – Power Management Control/Status Register
(Device #2)
Address Offset: D4h−D5h
Default Value: 0000h
Access: Read/Write, Read Only
Size: 16 bits
Bit Description
15 PME_Status ⎯RO: This bit is 0 to indicate that IGD does not support PME# generation from D3 (cold).
14:9 Reserved
8 PME_En⎯RO: This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled.
7:2 Reserved
1:0 PowerState⎯R/W: This field indicates the current power state of the IGD and can be used to set the
IGD into a new power state. If software attempts to Write an unsupported state to this field, Write
operation must complete normally on the bus, but the data is discarded and no state change occurs.
On a transition from D3 to D0 the graphics controller is optionally Reset to initial values.
Bits[1:0] Power State
00 D0 Default
01 D1
10 D2 Not Supported
11 D3
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