Datasheet

Register Description
R
120 Datasheet
4.11.16 INTRLINE – Interrupt Line Register (Device #2)
Address Offset: 3Ch
Default Value: 00h
Access: Read/Write
Size: 8 bits
Bit Description
7:0 Interrupt Connection: Used to communicate interrupt line routing information. POST software Writes
the routing information into this register as it initializes and configures the system. The value in this
register indicates which input of the System Interrupt controller that the device’s interrupt pin is connected
to.
4.11.17 INTRPIN – Interrupt Pin Register (Device #2)
Address Offset: 3Dh
Default Value: 01h
Access: Read Only
Size: 8 bits
Bit Description
7:0 Interrupt Pin: As a single function device, the IGD specifies INTA# as its interrupt pin. 01h=INTA#. For
Function #1, this register is set to 00h.
4.11.18 MINGNT – Minimum Grant Register (Device #2)
Address Offset: 3Eh
Default Value: 00h
Access: Read Only
Size: 8 bits
Bit Description
7:0 Minimum Grant Value: The IGD does not burst as a PCI compliant master.
4.11.19 MAXLAT – Maximum Latency Register (Device #2)
Address Offset: 3Fh
Default Value: 00h
Access: Read Only
Size: 8 bits
Bit Description
7:0 Maximum Latency Value: Bits[7:0]=00h. The IGD has no specific requirements for how often it needs to
access the PCI bus.