Datasheet

Register Description
R
Datasheet 117
4.11.8 MLT – Master Latency Timer Register (Device #2)
Address Offset: 0Dh
Default Value: 00h
Access: Read Only
Size: 8 bits
The IGD does not support the programmability of the master latency timer because it does not
perform bursts.
Bit Description
7:0 Master Latency Timer Count Value – RO
4.11.9 HDR – Header Type Register (Device #2)
Address Offset: 0Eh
Default Value: 00h
Access: Read Only
Size: 8 bits
This register contains the Header Type of the IGD.
Bit Description
7 Multi Function Status (MFunc): Indicates if the device is a multi-function device.
6:0 Header Code (H): This is a 7-bit value that indicates the Header code for the IGD. This code has the
value 00h, indicating a type 0 configuration space format.
4.11.10 GMADR – Graphics Memory Range Address Register
(Device #2)
Address Offset: 10−13h
Default Value: 00000008h
Access: Read/Write, Read Only
Size: 32 bits
IGD graphics system memory base address is specified in this register.
Bit Description
31:27 Memory Base Address⎯R/W: Set by the OS, these bits correspond to address signals [31:26].
26 128-MB Address Mask – RO: 0 indicates 128-MB address
25:4 Address Mask⎯RO: Indicates (at least) a 32-MB address range.
3 Prefetchable Memory⎯RO: Enable prefetching.
2:1 Memory Type⎯RO: Indicate 32-bit address.
0 Memory/IO Space⎯RO: Indicate System Memory Space.