Datasheet

Register Description
R
110 Datasheet
4.10.11 CAPPTR – Capabilities Pointer Register
Address Offset: 34h
Default Value: 00h
Access: Read Only
Size: 8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device capability in
the capability list.
Bit Description
7:0 Pointer to the offset of the first capability ID register block: In this case there are no capabilities
therefore these bits are hardwired to 00h to indicate the end of the capability-linked list.
4.10.12 HPLLCC – HPLL Clock Control Register (Device #0)
Address Offset: C0–C1h
Default Value: 00h
Access: Read Only
Size: 16 bits
Bit Description
15:11 Reserved
10 HPLL VCO Change Sequence Initiate Bit:
Software must Write a 0 to clear this bit and then Write a 1 to initiate sequence again.
9 Hphase Reset Bit:
1 = Assert
0 = Deassert (default)
8 Reserved
7:2 Reserved
1:0 HPLL Clock Control:
Software is allowed to update this register.
See
Table 29 below.