Specification Update

Summary Tables of Changes
12 Specification Update
Number D0 M0 Plans ERRATA
AN58 X
X
No Fix
MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data
after a Machine Check Exception (MCE)
AN59 X Fixed
Using Memory Type Aliasing with Memory Types WB/WT May Lead
to Unpredictable Behavior
AN60 X X No Fix
Code Breakpoint May Be Taken after POP SS Instruction if It Is
Followed by an Instruction that Faults
AN61 X X No Fix
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR
Image Leads to Partial Memory Update
AN62 X X No Fix Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
AN63 No Fix Erratum Removed
AN64 X X No Fix
Returning to Real Mode from SMM with EFLAGS.VM Set May Result
in Unpredictable System Behavior
AN65 X X No Fix
A Thermal Interrupt is Not Generated when the Current
Temperature is Invalid
AN66 X X No Fix Performance Monitoring Event FP_ASSIST May Not be Accurate
AN67 X X No Fix The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception
AN68 X X No Fix
BTM/BTS Branch-From Instruction Address May Be
Incorrect for Software Interrupts
AN69 Erratum removed
AN70 X X No Fix
Single Step Interrupts with Floating Point Exception Pending May Be
Mishandled
AN71 X X No Fix
Fault on ENTER Instruction May Result in Unexpected Values on
Stack Frame
AN72 Erratum removed
AN73 X X No Fix
Unaligned Accesses to Paging Structures May Cause the Processor
To Hang
AN74 No Fix Erratum Removed
AN75 X X No Fix
INVLPG Operation for Large (2M/4M) Pages May be Incomplete
Under Certain Conditions
AN76 X X No Fix
Page Access Bit May Be Set Prior to Signaling a Code Segment Limit
Fault
AN77 X Fixed
Performance Monitoring Events for Hardware Prefetch Requests
(4EH) and Hardware Prefetch Request Cache Misses (4FH) May Not
be Accurate
AN78 X X No Fix
EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after
Shutdown
AN79 X No Fix Erratum Removed
AN80 X X No Fix
Store Ordering May be Incorrect between WC and WP Memory
Types