Guide

System Memory Design Guidelines (DDR-SDRAM)
R
Intel
®
852GM Chipset Platform Design Guide 89
7.3.3.3. Clock Package Length Table
The package length data in the table below should be used to tune the motherboard length of each
SCLK/SCLK# clock pair between the GMCH and the associated SO-DIMM socket. Intel recommends
that die-pad to SO-DIMM pin length be tuned to within ± 25 mils in order to optimize timing margins
on the interface.
Table 34. DDR Clock Package Lengths
Signal Pin Number Package Length (mils)
SCLK_0 AB2 1177
SCLK#_0 AA2 1169
SCLK_1 AC26 840
SCLK#_1 AB25 838
SCLK_2 AC3 1129
SCLK#_2 AD4 1107
SCLK_3 AC2 1299
SCLK#_3 AD2 1305
SCLK_4 AB23 643
SCLK#_4 AB24 656
SCLK_5 AA3 1128
SCLK#_5 AB4 1146
Package length compensation can be performed on each individual clock output thereby matching total
length on SCK/SCK# exactly, or alternatively the average package length can be used for both outputs
of a pair and length tuning done with respect to the motherboard portion only.
7.3.3.4. Clock Routing Example
Figure 45 is an example of a board routing for the clock signal group.