Guide

System Memory Design Guidelines (DDR-SDRAM)
R
86 Intel
®
852GM Chipset Platform Design Guide
7.3.3. DDR Clock Routing Guidelines
Table 33. Clock Signal Group Routing Guidelines
Parameter Definition
Signal Group SCK[4,3,1,0] and SCK#[4,3,1,0]
Topology Differential Pair Point to Point
Reference Plane Ground Referenced
Single Ended Trace Impedance ( Zo ) 42 ohms ± 15%
Differential Mode Impedance (Zdiff) 70 ohms ± 15%
Nominal Trace Width
(see exceptions for breakout region below)
Inner Layers: 7 mils
Outer Layers: 8 mils (pin escapes only)
Nominal Pair Spacing (edge to edge)
(see exceptions for breakout region below)
Inner Layers: 4 mils
Outer Layers: 5 mils (pin escapes only)
Minimum Pair to Pair Spacing
(see exceptions for breakout region below)
20 mils
Minimum Serpentine Spacing 20 mils
Minimum Spacing to Other DDR Signals
(see exceptions for breakout region below)
20 mils
Minimum Isolation Spacing to non-DDR Signals 25 mils
Maximum Via Count 2 (per side)
Package Length Range – P1
1000 mils ± 350 mils
(See clock package length Table 34 for exact lengths.)
Trace Length Limits – L1 Max = 300 mils (breakout segment)
Total MB Length Limits – L1 + L2
Min = 0.5”
Max = 5.0”
Total Length – P1 + L1 + L2
Total length target is determined by placement (see Figure 43)
Total length for SO-DIMM0 group = X0 (see Figure 44)
Total length for SO-DIMM1 group = X1 (see Figure 44)
SCLK to SCLK# Length Matching Match total length to ±10 mils (see Section 7.3.3.1)
Clock to Clock Length Matching (Total Length)
Match all SO-DIMM0 clocks to X0 ± 25 mils (see Figure 44)
Match all SO-DIMM1 clocks to X1 ± 25 mils (see Figure 44)
Breakout Exceptions
(Reduced geometries for GMCH breakout region)
Inner Layers: 4 mil trace, 4 mil pair space allowed
Outer Layers: 5 mil trace, 5 mil pair space allowed
Pair to pair spacing of 5 mils allowed
Spacing to other DDR signals of 5 mils allowed
Maximum breakout length is 0.3”
NOTES:
1. Pad-to-Pin length tuning is utilized on clocks in order to achieve minimal variance. Package lengths range
between approximately 600 mils and 1400 mils. Exact package lengths for each clock signal are provided at
the end of this Section. Overall target length should be established based on placement and routing flow. The
resulting motherboard segment lengths must fall within the ranges specified.
2. The DDR clocks should be routed on internal layers, except for pin escapes. It is recommended that pin escape
vias be located directly adjacent to the ball pads on all clocks. Surface layer routing should be minimized.