Guide
R
8 Intel
®
852GM Chipset Platform Design Guide
10.9.2.5.1.
Terminating Unused Connections .............................. 187
10.9.2.5.2. Termination Plane Capacitance ................................. 187
10.9.3. Intel 82562ET/EM Disable Guidelines......................................................... 187
10.9.4. General Intel 82562ET/82562EM Differential Pair Trace Routing
Considerations............................................................................................. 188
10.9.4.1.1. Trace Geometry and Length ...................................... 189
10.9.4.1.2. Signal Isolation ........................................................... 190
10.9.4.1.3. Magnetics Module General Power and Ground Plane
Considerations............................................................ 190
10.9.4.2. Common Physical Layout Issues ................................................. 192
10.10. Power Management Interface ..................................................................................... 193
10.10.1. SYS_RESET# Usage Model ....................................................................... 193
10.10.2. PWRBTN# Usage Model............................................................................. 193
10.10.3. Power Well Isolation Control Strap Requirements ...................................... 193
10.11. CPU CMOS Considerations........................................................................................ 194
11. Platform Clock Routing Guidelines .......................................................................................... 197
11.1. System Clock Groups.................................................................................................. 197
11.2. Clock Group Topologies and Routing Constraints...................................................... 198
11.2.1. Host Clock Group ........................................................................................ 199
11.2.1.1. Host Clock Group General Routing Guidelines............................ 201
11.2.1.2. Clock to Clock Length Matching and Compensation ................... 201
11.2.1.3. EMI Constraints ............................................................................ 201
11.2.2. CLK66 Clock Group..................................................................................... 202
11.2.3. CLK33 Clock Group..................................................................................... 203
11.2.4. PCI Clock Group.......................................................................................... 204
11.2.5. CLK14 Clock Group..................................................................................... 205
11.2.6. DOTCLK Clock Group ................................................................................. 206
11.2.7. SSCCLK Clock Group ................................................................................. 207
11.2.8. USBCLK Clock Group ................................................................................. 208
11.3. CK-408 Clock Updates for Intel Celeron M Processor Platforms ............................... 209
11.4. CK-408 PWRDWN# Signal Connections.................................................................... 209
12. Intel 852GM Platform Power Delivery Guidelines.................................................................... 211
12.1. Definitions.................................................................................................................... 211
12.2. Platform Power Requirements .................................................................................... 211
12.2.1. Platform Power Delivery Architectural Block Diagram ................................ 212
12.3. Voltage Supply ............................................................................................................ 214
12.3.1. Power Management States ......................................................................... 214
12.3.2. Power Supply Rail Descriptions .................................................................. 214
12.4. Intel 852GM Platform Power-Up Sequence................................................................ 215
12.4.1. Processor Power Sequence Requirement .................................................. 215
12.4.2. GMCH Power Sequencing Requirements................................................... 215
12.4.3. ICH4-M Power Sequencing Requirements ................................................. 216
12.4.3.1. 3.3 V/1.5 V Power Sequencing..................................................... 218
12.4.3.2. V
5REF
Sequencing ......................................................................... 218
12.4.3.3. V
5REFSUS
Design Guidelines .......................................................... 219
12.4.4. DDR Memory Power Sequencing Requirements........................................ 220
12.5. Intel 852GM Platform Power Delivery Guidelines....................................................... 221
12.5.1. Processor Decoupling / Power Delivery Guidelines.................................... 221
12.5.2. Intel 852GM Decoupling Guidelines............................................................ 221
12.5.2.1. GMCH VCCSM Decoupling.......................................................... 222
12.5.2.2. DDR SDRAM VDD Decoupling .................................................... 223
12.5.2.3. DDR VTT Decoupling Placement and Layout Guidelines............ 223