Guide

Intel Celeron M Processor Front Side Bus Design Guidelines
R
Intel
®
852GM Chipset Platform Design Guide 73
Figure 33. Processor RESET# Signal Routing Example with ITP700FLEX Debug Port
CPU
GMCH
GND VIA
Layer 6
ITPFLEX
Connector
Secondary
Side
VCCP
Rs
Rtt
CPU
L2
L3
Rs
L1
ITPFLEX
CONNECTOR
MCH - M
Rtt
VCCP
RESET#
CPURESET#
RESET#
5.7. Processor and GMCH Host Clock Signals
Figure 34 illustrates processor and GMCH host clock signal routing. Both the processor and the
GMCH’s BCLK[1:0] signals are initially routed from the CK-408 clock generator on Layer 3.In the
recommended routing example (Figure 34) secondary side layer routing of BCLK[1:0] is 507 mils long.
To meet length-matching requirements between the processor and GMCH’s BCLK[1:0] signals, a
similar transition from Layer 3 to the secondary side layer is done next to the GMCH package outline.
Routing of the GMCH’s BCLK[1:0] signals on the secondary side is also trace tuned to 507 mils.
BCLK[1:0] layer transition vias are accompanied by GND stitching vias. For similar reasons, routing for
the ITP interposer’s BCLK[1:0] signals also transition from Layer 3 to the secondary side layer and have
507-mil long traces on this layer. Throughout the routing length on Layer 3, BCLK[1:0] signals should
reference a solid GND plane on Layer 2 and Layer 4 as shown in Figure 22.
If a system supports either the on-board ITP700FLEX connector or ITP interposer only, then differential
host clock routing to either the ITP700FLEX connector or CPU socket (but not both) is required.