Guide

Intel Celeron M Processor Front Side Bus Design Guidelines
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852GM Chipset Platform Design Guide
Figure 22. Layer 3 FSB Source Synchronous Signals
5.4.1. Source Synchronous Signal Length Matching Constraints
The routing guidelines presented in the following subsections define the recommended routing
topologies, trace width and spacing geometries, and absolute minimum and maximum routed lengths for
each signal group, which are recommended to achieve optimal SI and timing. In addition to the absolute
length limits provided in the individual guideline tables, more restrictive length matching requirements
called length-matching constraints. These additional requirements further restrict the minimum to
maximum length range of each signal group with respect to strobe, within the overall boundaries defined
in the guideline tables, as required to guarantee adequate timing margins. The amount of minimum to
maximum length variance allowed for each group around the strobe reference length varies from signal
group to signal group depending on the amount of timing variation, which can be tolerated.
5.4.2. Package Length Compensation
The Intel Celeron M processor package length does not need to be accounted for in the motherboard
routing since the processor has the source synchronous signals and the strobes length matched within the
group inside the package routing. However trace length matching of the GMCH package length does
need to be accounted for in the motherboard routing since the package does not have the source
synchronous signals and the strobes length matched within the group inside the package routing. See
Table 19 for the processor and the GMCH package lengths. Skew minimization requires GMCH die-pad
to processor pin (pad-to-pin) trace length matching of the FSB source synchronous signals that belong to
the same group including the strobe signals of that group.