Guide

Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines
R
42 Intel
®
852GM Chipset Platform Design Guide
Figure 12. Routing Illustration for Topology 1C
CPU
L1
L3
L2
Rs
3.3
390
390
L4
3.3
Q1
Q2
R1
R2
V_IO_RCVR
(System receiver)
VCCP
Rtt
Table 7. Layout Recommendations for Topology 1C
L1 L2 L3 L4 Rs R1 R2 Rtt Transmission
Line Type
0.5 –
12.0”
0 -
3.0”
0 –
3.0”
0.5 –
12.0”
330 Ω ± 5% 1.3 kΩ ± 5 % 330 Ω ± 5% 56 Ω ± 5% Micro-strip
0.5 –
12.0”
0 -
3.0”
0 –
3.0”
0.5 –
12.0”
330 Ω ± 5% 1.3 kΩ ± 5% 330 Ω ± 5% 56 Ω ± 5% Strip-line
4.3.4.4. Topology 2A: Open Drain (OD) Signals Driven by ICH4-M – PWRGOOD
The Topology 2A OD signal PWRGOOD should adhere to the following routing and layout
recommendations.
Table 8 lists the recommended routing requirements for the PWRGOOD signal of the Mobile Intel
Pentium 4 Processor–M. The routing guidelines allow the signal to be routed as either micro-strip or
strip-lines using 55 Ω ± 15% characteristic trace impedance. The pull-up voltage for termination resistor
Rtt is VCCP. Note that the Intel ICH4-M’s CPUPWRGD signal should be routed point-to-point to the
Mobile Intel Pentium 4 Processor–M’s PWRGOOD signal. The routing from the Mobile Intel Pentium 4
Processor–M’s PWRGOOD pin should fork out to both to the termination resistor, Rtt, and the ICH4-M.
Segments L1 and L2 from Figure 13 should not T-split from a trace from the Mobile Intel Pentium 4
Processor–M pin.