Guide

Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines
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40 Intel
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852GM Chipset Platform Design Guide
as either micro-strip or strip-lines using 55 Ω ± 15% characteristic trace impedance. The pull-up voltage
for termination resistor Rtt is VCCP.
Due to the dependencies on system design implementation, IERR# can be implemented in a number of
ways to meet design goals. IERR# can be routed as a test point or to any optional system receiver. It is
recommended that the FERR# signal of the Intel Mobile Intel Pentium 4 Processor–M be routed to the
FERR# signal of the Intel ICH4-M.
Figure 10. Routing Illustration for Topology 1A
L2
VCCP
L3
Rtt
L1
CPU
System
Receiver
Table 5. Layout Recommendations for Topology 1A
L1 L2 L3 Rtt Transmission Line Type
0.5” – 12.0” 0” – 3.0” 0” – 3.0” 56 Ω ± 5% Micro-strip
0.5” – 12.0” 0” – 3.0” 0” – 3.0” 56 Ω ± 5% Strip-line
4.3.4.2. Topology 1B: Open Drain (OD) Signals Driven by the Processor –
THERMTRIP#
The Topology 1B OD signal THERMTRIP# should adhere to the following routing and layout
recommendations. Table 6 lists the recommended routing requirements for the THERMTRIP# signals of
the Mobile Intel Pentium 4 Processor–M. The routing guidelines allow the signal to be routed as either
micro-strip or strip-lines using 55 Ω ± 15% characteristic trace impedance. The pull-up voltage for
termination resistor Rtt is VCCP.
THERMTRIP# can be implemented in a number of ways to meet design goals. It can be routed to the
ICH4-M or any optional system receiver. Intel recommneds that the THERMTRIP# signal of the Mobile
Intel Pentium 4 Processor–M be routed to the THRMTRIP# signal of the ICH4-M. The ICH4-M’s
THRMTRIP# signal is a new signal to the I/O controller hub architecture that allows the ICH4-M to
quickly put the whole system into an S5 state whenever the catastrophic thermal trip point has been
reached.