Guide

R
4 Intel
®
852GM Chipset Platform Design Guide
4.5.
Mobile Intel Pentium 4 Processor–M and Intel 852GM Chipset FSB Signal Package
Lengths .........................................................................................................................46
4.5.1. Mobile Intel Pentium 4 Processor-M GTLREF Layout and Routing
Recommendations......................................................................................... 50
4.5.2. AGTL+ I/O Buffer Compensation .................................................................. 50
4.5.2.1. Mobile Intel Pentium 4 Processor–M AGTL+ I/O Buffer
Compensation ................................................................................ 51
5. Intel Celeron M Processor Front Side Bus Design Guidelines .................................................. 52
5.1. Intel Celeron M Processor Front Side Bus Design Recommendations ........................ 52
5.2. Recommended Stack-up Routing and Spacing Assumptions ...................................... 52
5.2.1. Trace Space to Trace – Reference Plane Separation Ratio ......................... 52
5.2.2. Trace Space to Trace Width Ratio ................................................................ 53
5.3. Common Clock Signals ................................................................................................. 53
5.3.1. Processor Common Clock Signal Package Length Compensation .............. 54
5.4. Source Synchronous Signals General Routing Guidelines .......................................... 56
5.4.1. Source Synchronous Signal Length Matching Constraints ........................... 58
5.4.2. Package Length Compensation .................................................................... 58
5.4.3. Source Synchronous – Data Group .............................................................. 59
5.4.4. Source Synchronous – Address Group......................................................... 60
5.4.5. Intel Celeron M Processor and Intel 852GM Chipset GMCH FSB Signal
Package Lengths ........................................................................................... 61
5.5. Asynchronous Signals................................................................................................... 64
5.5.1. Topology 1A: Open Drain (OD) Signals Driven by the Processor – IERR#.. 65
5.5.2. Topology 1B: Open Drain (OD) Signals Driven by the Processor – FERR#
and THERMTRIP#......................................................................................... 65
5.5.3. Topology 1C: Open Drain (OD) Signals Driven by the Processor –
PROCHOT#................................................................................................... 66
5.5.4. Topology 2A: Open Drain (OD) Signals Driven by ICH4-M – PWRGOOD... 67
5.5.5. Topology 2B: CMOS Signals Driven by ICH4-M – DPSLP# ......................... 68
5.5.6. Topology 2C: CMOS Signals Driven by ICH4-M – LINT0/INTR, LINT1/NMI,
A20M#, IGNNE#, SLP#, SMI#, and STPCLK# ............................................. 68
5.5.7. Topology 3: CMOS Signals Driven by ICH4-M to CPU and FWH – INIT# ... 69
5.5.8. Voltage Translation Logic .............................................................................. 70
5.6. Processor RESET# Signal ............................................................................................ 71
5.6.1. Processor RESET# Routing Example........................................................... 72
5.7. Processor and GMCH Host Clock Signals.................................................................... 73
5.8. Processor GTLREF Layout and Routing Recommendations ....................................... 74
5.9. AGTL+ I/O Buffer Compensation .................................................................................. 76
5.9.1. Processor AGTL+ I/O Buffer Compensation ................................................. 76
5.10. Intel Celeron M Processor Front Side Bus Strapping and Debug Port......................... 79
5.11. Processor V
CCSENSE
/V
SSSENSE
Design Recommendations ............................................. 80
6. Processor Power Delivery Requirements .................................................................................. 81
7. System Memory Design Guidelines (DDR-SDRAM) ................................................................. 83
7.1. Length Matching and Length Formulas......................................................................... 84
7.2. Package Length Compensation .................................................................................... 84
7.3. Topologies and Routing Guidelines .............................................................................. 85
7.3.1. Clock Signals – SCK[4,3,1,0], SCK#[4,3,1,0]................................................ 85
7.3.2. Clock Topology Diagram ............................................................................... 85
7.3.3. DDR Clock Routing Guidelines ..................................................................... 86
7.3.3.1. Clock Length Matching Requirements ........................................... 87
7.3.3.2. Clock Reference Lengths ............................................................... 87