Guide

R
Intel
®
852GM Chipset Platform Design Guide 3
Contents
1. Introduction .................................................................................................................................19
1.1. Terminology ...................................................................................................................19
1.2. Referenced Documents .................................................................................................20
2. System Overview........................................................................................................................21
2.1. Intel
®
852GM Chipset Platform System Features .........................................................21
2.2. Processor Interface........................................................................................................22
2.2.1. Mobile Intel Celeron Processor......................................................................22
2.2.2. Mobile Intel Pentium 4 Processor-M ..............................................................23
2.2.3. Intel Celeron M Processor..............................................................................23
2.3. Intel 852GM Graphics Memory Controller Hub .............................................................24
2.3.1. Processor Front Side Bus Support ................................................................24
2.3.1.1. Integrated System Memory DRAM Controller ................................24
2.3.2. Integrated Graphics Controller.......................................................................24
2.3.2.1. Packaging/Power ............................................................................25
2.3.3. I/O Controller Hub (ICH4-M) ..........................................................................25
2.3.3.1. Packaging/Power ............................................................................26
3. General Design Considerations .................................................................................................27
3.1. Nominal Board Stack-Up ...............................................................................................27
3.2. Alternate Stack Ups .......................................................................................................29
4. Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design
Guidelines...................................................................................................................................31
4.1. Processor Front Side Bus (FSB) Routing Guidelines....................................................31
4.1.1. Return Path Evaluation ..................................................................................33
4.2. Processor Configuration ................................................................................................33
4.3. General Topology and Layout Design Guidelines.........................................................33
4.3.1. Source Synchronous (SS) Signal Group .......................................................34
4.3.1.1. Source Synchronous Data Group...................................................34
4.3.1.2. Source Synchronous Address Group .............................................35
4.3.2. FSB Data and Address Routing Example......................................................36
4.3.3. Common Clock (CC) AGTL+ Signal Group ...................................................39
4.3.4. Asynchronous AGTL+ Signals .......................................................................39
4.3.4.1. Topology 1A: Open Drain (OD) Signals Driven by the Processor –
IERR# and FERR#..........................................................................39
4.3.4.2. Topology 1B: Open Drain (OD) Signals Driven by the Processor –
THERMTRIP# .................................................................................40
4.3.4.3. Topology 1C: Open Drain (OD) Signals Driven by the Processor –
PROCHOT# ....................................................................................41
4.3.4.4. Topology 2A: Open Drain (OD) Signals Driven by ICH4-M –
PWRGOOD.....................................................................................42
4.3.4.5. Topology 2B: CMOS Signals Driven by ICH4-M – DPSLP# ..........43
4.3.4.6. Topology 2C: CMOS Signals Driven by ICH4-M – A20M#, IGNNE#,
LINT0/INTR, LINT1/NMI, SLP#, SMI#, and STPCLK# ...................44
4.3.4.7. Topology 3: CMOS Signals Driven by ICH4-M to CPU and FWH –
INIT#................................................................................................44
4.4. ITP Debug Port ..............................................................................................................45
4.4.1. Logic Analyzer Interface (LAI)........................................................................46
4.4.1.1. Mechanical Considerations.............................................................46
4.4.1.2. Electrical Considerations ................................................................46