Guide

Platform Design Checklist
R
Intel
®
852GM Chipset Platform Design Guide 259
Recommendations 9
• GPIO[25] can be used as AUDIO_PWRDN.
GPIO[43:32]:
• I/O pins. From main power well (V
CC
3_3).
• Default as outputs when enabled as GPIOs.
• These signals are NOT 5-V tolerant.
• GPIO[32] can be used as AGP_SUSPEND#.
• GPIO[33] can be used as KSC_VPPEN#.
• GPIO[34] can be used as SER_EN.
• GPIO[35] can be used as FWH_WP#.
• GPIO[36] can be used as FWH_TBL#.
• GPIO[40] can be used as IDE_PATADET.
• GPIO[41] can be used as IDE_SATADET.
14.8.3. AGP_BUSY# Design Requirement
Signal System
Pull-up/Pull-down
Notes
9
AGPBUSY#
10 K
Ω pull-up to
Vcc3_3
This ICH4-M signal requires a pull-up to the switched 3.3-V rail
(powered OFF during S3).
This ICH4-M signal must be connected to the AGP_BUSY# output
of GMCH.
NOTE: Please also consult Intel for the latest AGP Busy and Stop signal implementation.
14.8.4. (SMBus) System Management Interface
Pin Name System
Pull-up/Pull-down
Notes
9
SM_INTRUDER#
100 k
Ω pull-up to VccRTC
RTC well input requires pull-up (10 k-100 k) to reduce
leakage from coin cell battery in G3.
SMB_ALERT#/
GPIO[11]
10 k
Ω pull-up to
V3ALWAYS
SMBCLK,
SMBDATA,
SMLINK[1:0]
Pull-up to V3ALWAYS Require external pull-up resistors. Pull up value is
determined by bus characteristics. CRB schematics use
10 k
Ω pull-up resistors.
The SMBus and SMLink signals must be connected
together externally in S0 for SMBus 2.0 compliance:
SMBCLK connected to SMLink[0] and SMBDATA
connected to SMLink[1].