Guide

Platform Design Checklist
R
Intel
®
852GM Chipset Platform Design Guide 251
14.7.1.3. SODIMM Decoupling Recommendation
Pin Name F Qty Notes
9
Vcc1_25 0.1 µF
0.01 µF
Place one 0.1 µF cap and one 0.01 µF close to every 4 pull-up resistors
terminated to Vcc1_25 (VTT for DDR signal termination). In S3,
Vcc1_25 is powered OFF.
Vcc2_5Sus 0.1 µF
100-150 µF
9
4
A minimum of 9 high frequency caps are recommeneded to be placed
bewteen the SO-DIMMS. A minimum of 4 low frequency caps are
required.
14.7.2. FSB
Pin Name System
Pull-up/Pull-down
Notes
9
HXSWING,
HYSWING
301
Ω 1% pull-up to VCCP
150
Ω 1% pull-down to gnd
Signal voltage level = 1/3 of VCCP. C1a=0.1 µF.
C1b=0.1 µF. Trace should be 10-mil wide with 20-mil
spacing.
See Figure 142.
HXRCOMP,
HYRCOMP
27.4
Ω 1% pull down to gnd
One pulled-down resistor per pin. Trace should be 10-
mil wide with 20-mil spacing.
HDVREF[2:0]
49.9
Ω 1% pull-up to VCCP
100
Ω 1% pull-down to gnd
Signal voltage level = 2/3 of VCCP. Need one 0.1 µF
cap and one 1 µF cap for voltage divider.
HAVREF
49.9
Ω 1% pull-up to VCCP
100
Ω 1% pull-down to gnd
Signal voltage level = 2/3 of VCCP. Need one 0.1 µF
cap and one 1 µF cap for voltage divider.
HCCVREF
49.9
Ω 1% pull-up to VCCP
100
Ω 1% pull-down to gnd
Signal voltage level = 2/3 of VCCP. Need one 0.1 µF
cap and one 1 µF cap for voltage divider.
Figure 142. Intel 852GM GMCH HXSWING and HYSWING Reference Voltage Generation Circuit
301
R1
1%
150
1% C1a
+VCCP
GMCH
HXSWING
HXSWING HYSWING
301
1%
150
1%
C1b
+VCCP
HYSWING]