Guide

Platform Design Checklist
R
250 Intel
®
852GM Chipset Platform Design Guide
Pin Name System
Pull-up/Pull-down
Series
Resistor
Notes
9
VccSus2_5
60.4
Ω 1% pull-down to gnd
Need 0.1 µF cap by the voltage divider.
This signal may be optionally connected to
Vcc2_5 and powered off in S3.
Figure 141. Reference Voltage Level for SMVREF
+
-
VccSus2_5
10k
+
/
-
1%
10k+/-1 %
SMVREF
GMCH
SMVREF_0
0.1 uF
14.7.1.2. DDR SO-DIMM Interface
Pin Name Configuration Notes
9
VREF[2:1] Signal voltage level = VCCSus2_5 / 2.
VDD[33:1] Connect to VccSus2_5 Power must be provided during S3.
VDDSPD Connect to Vcc3_3
SA[2:0] Connect to either VC3_3 or
gnd
These lines are used for strapping the SPD address for
each SO-DIMM.
VSS[31:1] Connect to gnd
RESET(DU) Signal can be left as NC (“Not Connected)
VDDID Signal can be left as NC (“Not Connected)
DU[4:1] Signal can be left as NC (“Not Connected)
GND[1:0] Signal can be left as NC (“Not Connected)