Guide

Platform Design Checklist
R
246 Intel
®
852GM Chipset Platform Design Guide
Pin Name System
Pull-up/Pull-
down
Series
Termination
Voltage
Translation
Notes
9
VCCSENSE,
VSSSENSE
54.9
Ω ± 1%
pull-down to
gnd
(default: no
stuff)
For each signal, stuffing option for
pull-down should be provided for
testing purposes. Also, a test point for
differential probe ground should be
placed between the two resistors. For
normal operation, leave the resistors
unpopulated.
VSS[191:0] Connect to gnd
Figure 138. Routing Illustration for INIT# (for Intel Celeron M Processor)
CPU ICH4-M
L2
L3
L1
Rs
3.3V
3904
3904
FWH
L4
3.3V
Q1
Q2
R1
R2
V_IO_FWH
Figure 139. Voltage Translation Circuit for PROCHOT# (for Intel Celeron M Processor)
1.3K
+/-5%
330ohm
+/-5%
3.3V
To Receive
r
From Driver
3904
3904
Q1
Q2
3.3V
Rs
R1
R2
330ohm
+/-5%