Guide

Platform Design Checklist
R
244 Intel
®
852GM Chipset Platform Design Guide
Figure 137. Mobile Intel Pentium 4 Processor-M Power Up Sequence
RESET#
PWRGOOD
BCLK
Vcc
VID_GOOD
VID[4:0],
BSEL[1:0]
VCCVID
Tc
Td
Ta= 1us minimum (VCCVID > 1V to VID_GOOD high)
Tb= 50ms maximum (VID_GOOD to Vcc valid maximum time)
Tc= T37 (PWRGOOD inactive pulse width)
Td= T36 (PWRGOOD to RESET# de-assertion time)
Note: VID_GOOD is not a processor signal. This signal is routed to the
output enable pin of the voltage regluator control silicon. For more
information on implementation refer to the Intel Mobile Northwood
Processor and Intel 845MP Platform RDDP.
Ta Tb
14.5. Intel Celeron M Processor
14.5.1. Resistor Recommendations
Pin Name System
Pull-up/Pull-
down
Series
Termination
Voltage
Translation
Notes
9
A20M# Point-to-point connection to ICH4-M.
BR0# Point-to-point connection to GMCH.
COMP0,
COMP2
27.4
Ω ± 1%
pull-down to gnd
Resistor placed within 0.5” of
processor pin. Trace should be 27.4
Ω
± 15%.
COMP1,
COMP3
54.9
Ω ± 1%
pull-down to gnd
Resistor placed within 0.5” of
processor pin. Trace should be 55
Ω ±
15%.
DPSLP# Point-to-point connection to GMCH.
FER#
56
Ω pull-up to
VCCP
56 Ω from pull-
up to ICH4-M
pin.
Point-to-point connection to ICH4-M,
with pull-up resistor and series resistor
placed by ICH4-M.
GTLREF
1 K
Ω ± 1% pull-
up to VCCP
2 K
Ω ± 1% pull-
down to gnd
Voltage divider should be placed
within 0.5” of processor pin.