Guide

Intel 852GM Platform Power Delivery Guidelines
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216 Intel
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852GM Chipset Platform Design Guide
Figure 117. GMCH Power-Up Sequence
CPURST#
RSTIN#
1ms min
1ms max
PWROK
GMCH PWR
Rails
12.4.3. ICH4-M Power Sequencing Requirements
The following figure describes the power-up timing sequence for ICH4-M. The VGATE input should be
connected to the processor voltage regulator PWRGD output. When both PWROK and VGATE are
asserted, it indicates that core power and system power are stable and PCIRST# will be de-asserted a
minimum of 1 ms later. It is the responsibility of the system designer to ensure that the power and timing
requirements for the processor and GMCH are met.
Note: Please refer to ICH4-M datasheet for more details.