Guide

Intel 852GM Platform Power Delivery Guidelines
R
Intel
®
852GM Chipset Platform Design Guide 215
Signal Names Voltage
(V)
Current
(A)
Tolerance Enable Description
+V5S 5 1.0 ± 5% SLP_S3# - HIGH ICH4-M VREF,
MSE/KBD, FDD, IDE,
PCI
+V5ALWAYS 5 3.0 ± 5% +VDC ICH4-M VREFSUS,
USB Supply
+V12S 12 0.2 ± 5% SLP_S3# - HIGH PCI, IDE
+VCC_CORE /
+VCCP Mobile
Intel Pentium 4
processor-M
1.2 / 1.3 40.0 See IMVP-III +VCC_VID -HIGH Mobile Intel Pentium 4
processor-M I/O core
and I/O voltage by
IMVP-III VR
+VCC_CORE
Intel Celeron M
processor
1.356
(Standard)
1.004
(Ultra Low
Voltage)
32 ± 5% VID+ Intel Celeron M
processor core voltage
by IMVP – IV VR
± 10mV (ripple &
transient)
+VCCP
Intel Celeron M
processor
1.05 2.4 ± 5% VR_ON Intel Celeron M
processor I/O voltage
by IMVP-IV VR
+VCC_VID 1.2 0.300 + 5% DC
+ 9% AC
VR_ON Reference voltage for
Mobile Intel Pentium 4
processor-M PLL and
VID circuitry.
NOTE: GMCH VREF, DDR memory VREF, DDR termination, and GMCH TXLVDS can be turned off during S3.
12.4. Intel 852GM Platform Power-Up Sequence
The following sections describe the power-up timing sequence for Intel 852GM GMCH based
platforms.
12.4.1. Processor Power Sequence Requirement
Contact your Intel Field Representative for details on the Mobile Intel Pentium 4 Processor-M with
IMVP-III voltage regulator or Intel Celeron M processor with IMVP-IV voltage regulator.
12.4.2. GMCH Power Sequencing Requirements
All GMCH power rails should be stable before PWROK is asserted. The power rails can be brought up
in any order desired.
However, good design practice would have all GMCH power rails come up as
close in time as practical, with the core voltage (1.2 V) coming up first.
RSTIN#, which brings
GMCH out of reset, should be deasserted only after PWROK has been active for 1 ms. Once GMCH is
out of reset, it will deassert CPURST# within 1 ms.