Guide

Intel 852GM Platform Power Delivery Guidelines
R
214 Intel
®
852GM Chipset Platform Design Guide
12.3. Voltage Supply
12.3.1. Power Management States
Table 89. Power Management States on Intel Reference Board
Signal SLP_S1# SLP_S3# SLP_S4# SLP_S5# +V*ALW +V* +V*S Clocks
S0 (ON) HIGH HIGH HIGH HIGH ON ON ON ON
S1M (POS) LOW HIGH HIGH HIGH ON ON ON LOW
S3 (STR) LOW LOW HIGH HIGH ON ON OFF OFF
S4 (STD) LOW LOW LOW HIGH ON ON/OFF OFF OFF
S5 (Soft Off) LOW LOW LOW LOW ON OFF OFF OFF
12.3.2. Power Supply Rail Descriptions
Table 90. Power Supply Rail Descriptions on Intel Reference Board
Signal Names Voltage
(V)
Current
(A)
Tolerance Enable Description
SLP_S3# GMCH, DDR
Termination
+V1_25S 1.25 0.01 ± 3.2%
SLP_S4# DDR Reference (VREF)
+V1_5 1.5 0.03 ± 5% SLP_S4# - HIGH LAN logic
+V1_5S 1.5 1.35 ± 5% SLP_S3# - HIGH GMCHDVO-Core,
GMCH DLVDS, GMCH
DAC, GMCH ALVDS,
ICH4-M core, ICH4-M
VCCHL
+V1_5ALWAYS 1.5 0.1 ± 5% +V3ALWAYS ICH4-M Resume
+V1_2S 1.2 1.8 ± 5% SLP_S3# - HIGH GMCH Core, GMCH
HL, GMCH DPLL,
GMCH HPLL, GMCH
GPLL, GMCH VCCASM
+V2_5 2.5 8.12 ± 5% SLP_S4# - HIGH GMCH DDR I/O, DDR
SO-DIMM, GMCH
TXLVDS
1
+V3ALWAYS 3.3 0.4 ± 5% +VDC_ON ICH4-M Resume,
SMC/KBC, AC’97
+V3 3.3 0.9 ± 5% SLP_S4# - HIGH ICH4-M LAN I/O,
AC’97, RS232
+V3S 3.3 7.0 ± 5% SLP_S3# - HIGH GMCH GPIO, ICH4-M
I/O, CK-408, FWH,
SIO,PCI
+V5 5 9.0 ± 5% SLP_S4# - HIGH AC’97,