Guide

I/O Subsystem
R
188 Intel
®
852GM Chipset Platform Design Guide
Figure 101. Intel 82562ET/EM Disable Circuitry
Intel® 82562EM/ET Disable
3.3V Sus
10K 5%
10K 5%
LAN_RST#
GPIO_LAN_ENABLE MMBT3906
There are four pins which are used to put the Intel 82562ET/EM controller in different operating states:
Test_En, Isol_Tck, Isol_Ti, and Isol_Tex. The table below describes the operational and disable features
for this design.
The four control signals shown in the below table should be configured as follows: Test_En should be
pulled-down through a 100-
Ω resistor. The remaining three control signals should each be connected
through 100-
Ω series resistors to the common node “Intel 82562ET/EM _Disable” of the disable circuit.
Table 77. Intel 82562ET/EM Control Signals
Test_En Isol_Tck Isol_Ti Isol_Tex State
0 0 0 0 Enabled
0 1 1 1 Disabled w/ Clock (low power)
1 1 1 1 Disabled w/out Clock (lowest power)
In addition, if the LAN Connect Interface of the ICH4-M is not used, the VccLAN1_5 and the
VccLAN3_3 are still required to be powered during normal operating states. It is acceptable to power
the VccLAN1_5 and VccLAN3_3 power pins by the same switched voltage source that supplies power
to the Vcc1_5 and Vcc3_3 power pins. Also, the LAN_RST# pin of the ICH4-M should be pulled-down
to GND with a 10-k
Ω to keep the interface disabled.
10.9.4. General Intel 82562ET/82562EM Differential Pair Trace Routing
Considerations
Trace routing considerations are important to minimize the effects of crosstalk and propagation delays
on sections of the board where high-speed signals exist. Signal traces should be kept as short as possible
to decrease interference from other signals, including those propagated through power and ground
planes.
Observe the following suggestions to help optimize board performance.
Note: Some suggestions are specific to a 4.3-mil stack-up
• Maintain constant symmetry and spacing between the traces within a differential pair.
• Keep the signal trace lengths of a differential pair equal to each other.