Guide

I/O Subsystem
R
Intel
®
852GM Chipset Platform Design Guide 187
together. This will result in a smaller loop area and reduce the likelihood of crosstalk. The effect of
different configurations on the amount of crosstalk can be studied using electronics modeling software.
10.9.2.5.1. Terminating Unused Connections
In Ethernet designs, it is common practice to terminate unused connections on the RJ-45 connector and
the magnetics module to ground. Depending on overall shielding and grounding design, this may be
done to the chassis ground, signal ground, or a termination plane. Care must be taken when using
various grounding methods to insure that emission requirements are met. The method most often
implemented is called the “Bob Smith” Termination. In this method, a floating termination plane is cut
out of a power plane layer. This floating plane acts as a plate of a capacitor with an adjacent ground
plane. The signals can be routed through 75-
Ω resistors to the plane. Stray energy on unused pins is then
carried to the plane.
10.9.2.5.2. Termination Plane Capacitance
Intel recommends that the termination plane capacitance equals a minimum value of 1500 pF. This helps
reduce the amount of crosstalk on the differential pairs (TDP/TDN and RDP/RDN) from the unused
pairs of the RJ-45. Pads may be placed for an additional capacitance to chassis ground, which may be
required if the termination plane capacitance is not large enough to pass EFT (Electrical Fast Transient)
testing. If a discrete capacitor is used, to meet the EFT requirements it should be rated for at least 1000
Vac.
Figure 100. Termination Plane
N/C
RJ-45
Magnetics Module
RDP
RDN
TDP
TDN
Termination Plane
A
ddition Capacitance that may need to be
added for EFT testing
10.9.3. Intel 82562ET/EM Disable Guidelines
To disable the Intel 82562ET/EM, the device must be isolated (disabled) prior to reset (RSM_PWROK)
asserting. Using a GPIO, such as GPO28 to be LAN_Enable (enabled high), LAN will default to
enabled on initial power-up and after an AC power loss. This circuit shown below will allow this
behavior. The BIOS controlling the GPIO can disable the LAN micro-controller.