Guide

I/O Subsystem
R
158 Intel
®
852GM Chipset Platform Design Guide
10.2. PCI
The ICH4-M provides a PCI Bus interface that is compliant with the PCI Local Bus Specification
Revision 2.2
. The implementation is optimized for high performance data streaming when the ICH4-M
is acting as either the target or the initiator in the PCI bus.
The ICH4-M supports six PCI Bus masters (excluding the ICH4-M), by providing six REQ#/GNT#
pairs. In addition, the ICH4-M supports two PC/PCI REQ#/GNT# pairs, one of which is multiplexed
with a PCI REQ#/GNT# pair.
Figure 75. PCI Bus Layout Example
ICH4-M
1
2
3
4
5
6
L1
L2
L3
L4
L5
L6
10.3. AC’97
The ICH4-M implements an AC’97 2.1, 2.2, and 2.3 compliant digital controller. Please contact your
codec IHV (Independent Hardware Vendor) for information on 2.2 compliant products. The AC’97 2.2
specification is on the Intel website:
http://developer.intel.com/ial/scalableplatforms/audio/index.htm - 97spec/
The AC-link is a bi-directional, serial PCM digital stream. It handles multiple input and output data
streams, as well as control register accesses that employs a time division multiplexed (TDM) scheme.
The AC-link architecture provides for data transfer through individual frames transmitted in a serial
fashion. Each frame is divided into 12 outgoing and 12 incoming data streams or slots. The architecture
of the ICH4-M AC-link allows a maximum of three codecs to be connected. Figure 76 shows a three-
codec topology of the AC-link for the ICH4-M.