Guide

I/O Subsystem
R
Intel
®
852GM Chipset Platform Design Guide 155
10.1.3. Secondary IDE Connector Requirements
Figure 74. Connection Requirements for Secondary IDE Connector
ICH4-M
Secondary I
D
PCIRST#
†
SDD[15:0]
SDA[2:0]
SDCS[3,1]
#
SDIOR#
SDDRE
Q
SDDACK#
SDIOW
#
SIORDY (SRDSTB / SWDMARDY# )
4.7
k
8.2~10
k
3.3
V
3.3
V
SDIAG# / CBLID
#
IRQ[15]
GPIO
y
CSEL
10 k
22 – 47
Ω
†
Due to ringing,
PCIRST# must be
b
uffere
d
• 22 Ω - 47 Ω series resistors are required on RESET#. The correct value should be determined for
each unique motherboard design, based on signal quality.
• An 8.2 kΩ - 10 kΩ pull-up resistor is required on IRQ15 to VCC3_3.
• A 4.7-kΩ, pull-up resistor to VCC3_3 is required on SIORDY.
• Series resistors can be placed on the control and data line to improve signal quality. The resistors
are placed as close to the connector as possible. Values are determined for each unique
motherboard design.
• The 10-kΩ resistor to ground on the SDIAG#/CBLID# signal is required on the Secondary
Connector. This change is to prevent the GPI pin from floating if a device is not present on the IDE
interface.
10.1.4. Mobile IDE Swap Bay Support
Systems that require the support for an IDE “hot” swap drive bay can be designed to utilize the tri-state
feature of the ICH4-M’s IDE interface to achieve this functionality. To support a mobile “hot” sway
bay, the ICH4-M allows the IDE output signals to be tri-stated and input buffers to be turned off. This
requires certain hardware and software requirements to be met for proper operation.
From a hardware perspective a minimum of two spare control signals (i.e. GPIO’s) and a FET are
needed to properly utilize the IDE tri-state feature. An IDE drive must have a reset signal (i.e. first