Guide

System Memory Design Guidelines (DDR-SDRAM)
R
104 Intel
®
852GM Chipset Platform Design Guide
Figure 51. Control Signal to Clock Trace Length Matching Diagram
SO-DIMM0
GMCH Package
SCS#[1:0]
SCKE[1:0]
SCK[1:0]
SCK#[1:0]
Note: All lengths are measured from GMCH
die pad to SO-DIMM connector pads.
CNTRL Length = Y0
Clock Ref. Length = X0
SO-DIMM0 SO-DIMM1
SCK[4:3]
SCK#[4:3]
Clock Ref. Length = X1
Note: All lengths are measured from GMCH
die pad to SO-DIMM connector pads.
SCS#[3:2]
SCKE[3:2]
CNTRL Length = Y1
(X0 – 1.0" ) <= Y0 <= (X0 + 0.5")
(X1 – 1.0") <= Y1 <= (X1+ 0.5")
GMCH Package
GMCH
Die
GMCH
Die