Datasheet

Processor Configuration Registers
84 Datasheet, Volume 2
90–91h MSI_CAPID Message Signaled Interrupts Capability ID A005h RO
92–93h MC Message Control 0000h RO, RW
94–97h MA Message Address 0000_0000h RW, RO
98–99h MD Message Data 0000h RW
9A–9Fh RSVD Reserved 0h RO
A0–A1h PEG_CAPL PCI Express-G Capability List 0010h RO
A2–A3h PEG_CAP PCI Express-G Capabilities 0142h RO, RW-O
A4–A7h DCAP Device Capabilities 0000_8000h RO, RW-O
A8–A9h DCTL Device Control 0000h RO, RW
AA–ABh DSTS Device Status 0000h RW1C, RO
AC–AFh RSVD Reserved 0h RO
B0–B1h LCTL
Link Control
0000h
RW, RO,
RW-V
B2–B3h LSTS
Link Status
1001h
RO-V,
RW1C, RO
B4–B7h SLOTCAP Slot Capabilities 0004_0000h RW-O, RO
B8–B9h SLOTCTL Slot Control 0000h RO
BA–BBh SLOTSTS
Slot Status
0000h
RO, RO-V,
RW1C
BC–BDh RCTL Root Control 0000h RO, RW
BE–C3h RSVD Reserved 0h RO
C4–C7h RSVD Reserved 0000_0800h RO, RW-O
C8–C9h RSVD Reserved 0000h RW-V, RW
CA–CFh RSVD Reserved 0h RO
D0–D1h LCTL2
Link Control 2
0002h
RWS,
RWS-V
D2–D3h RSVD Reserved 0000h RO-V
Table 2-8. PCI Device 1, Function 0–2 Configuration Register Address Map (Sheet 2 of 2)
Address
Offset
Register
Symbol
Register Name
Reset
Value
Access