Datasheet

Datasheet, Volume 2 83
Processor Configuration Registers
2.6 PCI Device 1, Function 0–2 Configuration
Registers
Table 2-8 lists the registers arranged by address offset. Register bit descriptions are in
the sections following the table.
Table 2-8. PCI Device 1, Function 0–2 Configuration Register Address Map (Sheet 1 of 2)
Address
Offset
Register
Symbol
Register Name
Reset
Value
Access
0–1h VID1 Vendor Identification 8086h RO
2–3h DID1
Device Identification See
Section 2.2
RO-FW
4–5h PCICMD1 PCI Command 0000h RW, RO
6–7h PCISTS1
PCI Status
0010h
RW1C, RO,
RO-V
8h RID1 Revision Identification 00h RO-FW
9–Bh CC1 Class Code 06_0400h RO
Ch CL1 Cache Line Size 00h RW
Dh RSVD Reserved 0h RO
Eh HDR1 Header Type 81h RO
F–17h RSVD Reserved 0h RO
18h PBUSN1 Primary Bus Number 00h RO
19h SBUSN1 Secondary Bus Number 00h RW
1Ah SUBUSN1 Subordinate Bus Number 00h RW
1Bh RSVD Reserved 0h RO
1Ch IOBASE1 I/O Base Address F0h RW
1Dh IOLIMIT1 I/O Limit Address 00h RW
1E–1Fh SSTS1 Secondary Status 0000h RW1C, RO
20–21h MBASE1 Memory Base Address FFF0h RW
22–23h MLIMIT1 Memory Limit Address 0000h RW
24–25h PMBASE1 Prefetchable Memory Base Address FFF1h RW, RO
26–27h PMLIMIT1 Prefetchable Memory Limit Address 0001h RW, RO
28–2Bh PMBASEU1 Prefetchable Memory Base Address Upper 0000_0000h RW
2C–2Fh PMLIMITU1 Prefetchable Memory Limit Address Upper 0000_0000h RW
30–33h RSVD Reserved 0h RO
34h CAPPTR1 Capabilities Pointer 88h RO
35–3Bh RSVD Reserved 0h RO
3Ch INTRLINE1 Interrupt Line 00h RW
3Dh INTRPIN1 Interrupt Pin 01h RW-O, RO
3E–3Fh BCTRL1 Bridge Control 0000h RW, RO
40–7Fh RSVD Reserved 0h RO
80–83h PM_CAPID1 Power Management Capabilities C803_9001h RO, RO-V
84–87h PM_CS1 Power Management Control/Status 0000_0008h RO, RW
88–8Bh SS_CAPID Subsystem ID and Vendor ID Capabilities 0000_800Dh RO
8C–8Fh SS Subsystem ID and Subsystem Vendor ID 0000_8086h RW-O