Datasheet

Processor Configuration Registers
74 Datasheet, Volume 2
2.5.24 REMAPBASE—Remap Base Address Register
2.5.25 REMAPLIMIT—Remap Limit Address Register
B/D/F/Type: 0/0/0/PCI
Address Offset: 90–97h
Reset Value: 0000_000F_FFF0_0000h
Access: RW-KL, RW-L
Size: 64 bits
BIOS Optimal Default 0000_0000_0000h
Bit Attr
Reset
Value
RST/
PWR
Description
63:36 RO 0h Reserved
35:20 RW-L FFFFh Uncore
Remap Base Address (REMAPBASE)
The value in this register defines the lower boundary of the Remap
window. The Remap window is inclusive of this address. In the
decoder A[19:0] of the Remap Base Address are assumed to be 0s.
Thus, the bottom of the defined memory range will be aligned to a
1 MB boundary.
When the value in this register is greater than the value
programmed into the Remap Limit register, the Remap window is
disabled.
These bits are Intel TXT lockable.
19:1 RO 0h Reserved
0RW-KL 0b Uncore
Lock (LOCK)
This bit will lock all writeable settings in this register, including
itself.
B/D/F/Type: 0/0/0/PCI
Address Offset: 98–9Fh
Reset Value: 0000_0000_0000_0000h
Access: RW-KL, RW-L
Size: 64 bits
BIOS Optimal Default 0000_0000_0000h
Bit Attr
Reset
Value
RST/
PWR
Description
63:36 RO 0h Reserved
35:20 RW-L 0000h Uncore
Remap Limit Address (REMAPLMT)
The value in this register defines the upper boundary of the Remap
window. The Remap window is inclusive of this address. In the
decoder A[19:0] of the remap limit address are assumed to be Fs.
Thus, the top of the defined range will be one byte less than a
1 MB boundary.
When the value in this register is less than the value programmed
into the Remap Base register, the Remap window is disabled.
These Bits are Intel TXT lockable.
19:1 RO 0h Reserved
0RW-KL 0b Uncore
Lock (LOCK)
This bit will lock all writeable settings in this register, including
itself.