Datasheet

Datasheet, Volume 2 7
2.12.14 DMIESD—DMI Element Self Description Register ................................... 196
2.12.15 DMILE1D—DMI Link Entry 1 Description Register................................... 197
2.12.16 DMILE1A—DMI Link Entry 1 Address Register........................................ 197
2.12.17 DMILE2D—DMI Link Entry 2 Description Register................................... 198
2.12.18 DMILE2A—DMI Link Entry 2 Address Register........................................ 198
2.12.19 LCAP—Link Capabilities Register.......................................................... 199
2.12.20 LCTL—Link Control Register................................................................ 200
2.12.21 LSTS—DMI Link Status Register .......................................................... 201
2.12.22 LCTL2—Link Control 2 Register ........................................................... 202
2.12.23 LSTS2—Link Status 2 Register ............................................................ 204
2.12.24 AFE_BMUF0—AFE BMU Configuration Function 0 Register ....................... 204
2.12.25 AFE_BMUT0—AFE BMU Configuration Test 0 Register ............................. 204
2.13 MCHBAR Registers in Memory Controller – Channel 0........................................... 205
2.13.1 TC_DBP_C0—Timing of DDR Bin Parameters Register............................. 205
2.13.2 TC_RAP_C0—Timing of DDR Regular Access Parameters Register ............ 206
2.13.3 SC_IO_LATENCY_C0—IO Latency Configuration Register ........................ 206
2.13.4 TC_SRFTP_C0—Self-Refresh Timing Parameters Register........................ 207
2.13.5 PM_PDWN_config_C0—Power-down Configuration Register..................... 207
2.13.6 TC_RFP_C0—Refresh Parameters Register............................................ 208
2.13.7 TC_RFTP_C0—Refresh Timing Parameters Register ................................ 208
2.14 MCHBAR Registers in Memory Controller – Channel 1........................................... 209
2.14.1 TC_DBP_C1—Timing of DDR Bin Parameters Register............................. 209
2.14.2 TC_RAP_C1—Timing of DDR Regular Access Parameters Register ............ 210
2.14.3 SC_IO_LATENCY_C1—IO Latency Configuration Register ........................ 210
2.14.4 TC_SRFTP_C1—Self-Refresh Timing Parameters Register........................ 211
2.14.5 PM_PDWN_Config_C1—Power-down Configuration Register..................... 211
2.14.6 TC_RFP_C1—Refresh Parameters Register............................................ 212
2.14.7 TC_RFTP_C1—Refresh Timing Parameters Register ................................ 212
2.15 MCHBAR Registers in Memory Controller –
Integrated Memory Peripheral Hub (IMPH).......................................................... 213
2.15.1 CRDTCTL3—Credit Control 3 Register................................................... 213
2.16 MCHBAR Registers in Memory Controller – Common............................................. 214
2.16.1 MAD_CHNL—Address Decoder Channel Configuration Register................. 214
2.16.2 MAD_DIMM_ch0—Address Decode Channel 0 Register............................ 215
2.16.3 MAD_DIMM_ch1—Address Decode Channel 1 Register............................ 216
2.16.4 PM_SREF_config—Self Refresh Configuration Register ............................ 217
2.17 Memory Controller MMIO Registers Broadcast Group............................................ 218
2.17.1 PM_PDWN_Config—Power-down Configuration Register.......................... 218
2.17.2 PM_CMD_PWR—Power Management Command Power Register................ 219
2.17.3 PM_BW_LIMIT_config—BW Limit Configuration Register ......................... 219
2.18 Integrated Graphics VT-d Remapping Engine Registers......................................... 220
2.18.1 VER_REG—Version Register................................................................ 221
2.18.2 CAP_REG—Capability Register............................................................. 222
2.18.3 ECAP_REG—Extended Capability Register............................................. 225
2.18.4 GCMD_REG—Global Command Register................................................ 226
2.18.5 GSTS_REG—Global Status Register...................................................... 230
2.18.6 RTADDR_REG—Root-Entry Table Address Register................................. 231
2.18.7 CCMD_REG—Context Command Register.............................................. 232
2.18.8 FSTS_REG—Fault Status Register........................................................ 234
2.18.9 FECTL_REG—Fault Event Control Register............................................. 236
2.18.10 FEDATA_REG—Fault Event Data Register.............................................. 237
2.18.11 FEADDR_REG—Fault Event Address Register......................................... 237
2.18.12 FEUADDR_REG—Fault Event Upper Address Register.............................. 237
2.18.13 AFLOG_REG—Advanced Fault Log Register ........................................... 238
2.18.14 PMEN_REG—Protected Memory Enable Register..................................... 239
2.18.15 PLMBASE_REG—Protected Low-Memory Base Register ........................... 240