Datasheet

Processor Configuration Registers
58 Datasheet, Volume 2
2RO 0h Reserved
1RW-L 0bUncore
IGD VGA Disable (IVD)
0 = Enable. Device 2 (IGD) claims VGA memory and I/O cycles,
the Sub-Class Code within Device 2 Class Code register is 00.
1 = Disable. Device 2 (IGD) does not claim VGA cycles (Memory
and I/O), and the Sub- Class Code field within Device 2
function 0 Class Code register is 80h.
BIOS Requirement: BIOS must not set this bit to 0 if the GMS
field (bits 7:3 of this register) pre-allocates no memory.
This bit MUST be set to 1 if Device 2 is disabled using a register
(DEVEN[3] = 0).
This register is locked by Intel TXT lock.
0RW-KL 0b Uncore
GGC Lock (GGCLCK)
When set to 1b, this bit will lock all bits in this register.
B/D/F/Type: 0/0/0/PCI
Address Offset: 50–51h
Reset Value: 0028h
Access: RW-KL, RW-L
Size: 16 bits
BIOS Optimal Default 00h
Bit Attr
Reset
Value
RST/
PWR
Description