Datasheet

4 Datasheet, Volume 2
2.5.8 SVID—Subsystem Vendor Identification Register......................................54
2.5.9 SID—Subsystem Identification Register ..................................................54
2.5.10 PXPEPBAR—PCI Express Egress Port Base Address Register.......................55
2.5.11 MCHBAR—Host Memory Mapped Register Range Base Register ..................56
2.5.12 GGC—GMCH Graphics Control Register Register.......................................57
2.5.13 DEVEN—Device Enable Register.............................................................59
2.5.14 PCIEXBAR—PCI Express Register Range Base Address Register..................60
2.5.15 DMIBAR—Root Complex Register Range Base Address Register..................62
2.5.16 PAM0—Programmable Attribute Map 0 Register .......................................63
2.5.17 PAM1—Programmable Attribute Map 1 Register .......................................64
2.5.18 PAM2—Programmable Attribute Map 2 Register .......................................65
2.5.19 PAM3—Programmable Attribute Map 3 Register .......................................66
2.5.20 PAM4—Programmable Attribute Map 4 Register .......................................67
2.5.21 PAM5—Programmable Attribute Map 5 Register .......................................68
2.5.22 PAM6—Programmable Attribute Map 6 Register .......................................69
2.5.23 LAC—Legacy Access Control Register......................................................70
2.5.24 REMAPBASE—Remap Base Address Register............................................74
2.5.25 REMAPLIMIT—Remap Limit Address Register...........................................74
2.5.26 TOM—Top of Memory Register...............................................................75
2.5.27 TOUUD—Top of Upper Usable DRAM Register ..........................................76
2.5.28 BDSM—Base Data of Stolen Memory Register..........................................77
2.5.29 BGSM—Base of GTT stolen Memory Register ...........................................77
2.5.30 G Memory Base Register.......................................................................78
2.5.31 TOLUD—Top of Low Usable DRAM Register..............................................79
2.5.32 SKPD—Scratchpad Data Register...........................................................80
2.5.33 CAPID0_A—Capabilities A Register.........................................................81
2.6 PCI Device 1, Function 0–2 Configuration Registers................................................83
2.6.1 VID1—Vendor Identification Register......................................................85
2.6.2 DID1—Device Identification Register ......................................................85
2.6.3 PCICMD1—PCI Command Register.........................................................86
2.6.4 PCISTS1—PCI Status Register ...............................................................88
2.6.5 RID1—Revision Identification Register ....................................................90
2.6.6 CC1—Class Code Register.....................................................................90
2.6.7 CL1—Cache Line Size Register...............................................................91
2.6.8 HDR1—Header Type Register ................................................................91
2.6.9 PBUSN1—Primary Bus Number Register..................................................91
2.6.10 SBUSN1—Secondary Bus Number Register..............................................92
2.6.11 SUBUSN1—Subordinate Bus Number Register .........................................92
2.6.12 IOBASE1—I/O Base Address Register .....................................................93
2.6.13 IOLIMIT1—I/O Limit Address Register ....................................................93
2.6.14 SSTS1—Secondary Status Register ........................................................94
2.6.15 MBASE1—Memory Base Address Register................................................95
2.6.16 MLIMIT1—Memory Limit Address Register...............................................96
2.6.17 PMBASE1—Prefetchable Memory Base Address Register............................97
2.6.18 PMLIMIT1—Prefetchable Memory Limit Address Register ...........................98
2.6.19 PMBASEU1—Prefetchable Memory Base Address Upper Register.................99
2.6.20 PMLIMITU1—Prefetchable Memory Limit Address Upper Register..............100
2.6.21 CAPPTR1—Capabilities Pointer Register.................................................100
2.6.22 INTRLINE1—Interrupt Line Register .....................................................101
2.6.23 INTRPIN1—Interrupt Pin Register.........................................................101
2.6.24 BCTRL1—Bridge Control Register.........................................................102
2.6.25 PM_CAPID1—Power Management Capabilities Register ...........................104
2.6.26 PM_CS1—Power Management Control/Status Register ............................105
2.6.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities Register................106
2.6.28 SS—Subsystem ID and Subsystem Vendor ID Register ...........................107
2.6.29 MSI_CAPID—Message Signaled Interrupts Capability ID Register .............107